Name :Reset/set triggers

Symbol:RS

Illustrate:

        You can use the Reset Bit Trigger command to reset or set the operand bit based on the signal state of the input R1 and S1. If the signal status of input R1 is "1" and the signal status of input S1 is "0", the specified operand is reset to "0". If the signal status of input R1 is "0" and the signal status of input S1 is "1", the specified operand is set to "1".
        Input R1 takes precedence over input S1. When the signal status of input S1 and R1 is both "1", the signal state of the specified operand is reset to "0".
        If both inputs R1 and S1 have a signal status of "0", the command will not be executed. Therefore, the signal state of the operand remains the same.
        The current signal status of the operand is transmitted to the output Q, where it can be queried.

Image:

Parameter:

Parameter | Statement | Type | Description
--- | --- | --- | ---
R1 | Input | BOOL |
    Enable reset
S1 | Input | BOOL |
    Enable set
Q1 | Output | BOOL |
    The signal status of the operand

Example:

LD:

ST:

RS_inst1(S1 := TagIn1, R1 := TagIn2, Q1 => TagOut);

Interpretation:

    When one of the following conditions is met, the operand "TagOut" is reset:
    ●The signal status of the operand "TagIn1" is "0", and the signal status of the operand "TagIn_2" is "1"
    ●The signal status of the operands "TagIn1" and "TagIn2" is "1".
    The TagOut operand is set when the following conditions are met:
    ●The signal status of the operand "TagIn2" is "0", and the signal status of the operand "TagIn1" is "1".